Fully-depleted SOI CMOS circuits and technology for ultra-low power applications </titleInfo> <name type="personal"> <namePart>桜井, 貴康</namePart> <role> <roleTerm type="text" authority="marcrelator">creator</roleTerm> </role> </name> <name type="personal"> <namePart>Matsuzawa, Akira</namePart> <role> <roleTerm type="text" authority="marcrelator">creator</roleTerm> </role> </name> <name type="personal"> <namePart>Douseki, Takakuni</namePart> <role> <roleTerm type="text" authority="marcrelator">creator</roleTerm> </role> </name> <typeOfResource>text</typeOfResource> <originInfo> <publisher>Springer</publisher> <dateIssued/> <frequency>unknown</frequency> </originInfo> <language> <languageTerm authority="iso639-2b" type="code">eng</languageTerm> </language> <physicalDescription> <form authority="marcform">volume</form> <extent>xv, 411 p. ; 25 cm</extent> </physicalDescription> <subject> </subject> <classification authority="udc">621.3</classification> <abstract/> <note>"The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society"--P. 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